1. Field of the Invention
The present invention relates to a semiconductor device and to a method for manufacturing the same, particularly to a semiconductor device provided with multi-layered wiring and to a method for manufacturing the same.
2. Description of Related Art
With the development of highly efficient semiconductor devices, a multiple wiring layer is becoming common these days. When forming the multiple wiring layer, it is important to keep good reliability of the product by leveling an interlayer insulation film and hence improving the covering capacity of the wiring metal. As the interlayer insulation film, a silicon oxide film or a silicon nitride film deposited by CVD (Chemical Vapor Deposition) method or plasma CVD (Plasma Enhanced Chemical Vapor Deposition) method is widely used.
However, since the insulation film made by any of these methods is liable to be formed with further enlarged unevenness due to the lower wiring layer, forming an upper wiring layer thereon becomes limited. In order to offset this drawback, a method for leveling the surface of the lower wiring layer by applying a silica film or an organic silica film is disclosed, for instance, in Japanese Patent Laid-open No. 124246/83 or Japanese Patent Laid-open No. 100748/82.
FIG. 1 is a vertical crosssectional view of a semiconductor chip showing an example of the leveling method of an interlayer insulation film of the prior art, in which a portion of the interlayer insulation film is made of an organic silica film made by the rotary application method.
In the leveling method of this interlayer insulation film, lower wiring layer 3 made of, for example, aluminum is first formed on field insulation film 2 prepared on semiconductor substrate 1. Then, CVD insulation film 4, such as a silicon nitride film, is formed on wiring layer 3 to make the metallic film and the organic silica film contact closely. Thereafter, organic silica film 5 is processed into a desired thickness by rotary application and heat treatment to form a flat interlayer insulation film, on which upper wiring layer 6 made of, for example, aluminum is formed.
With the leveling method of the interlayer insulation film of the conventional type, although the metallic film used in the method for the upper wiring layer has a favorable covering capacity, it only smoothes the corner of convex parts of the lower wiring layer, so that the height of the layer from the surface of the semiconductor substrate becomes different as the layers of wiring increase in number depending on the area where the wiring layers are densely or sparsely disposed. Since this height difference readily exceeds the focus margin of lithography, the pattern accuracy of the upper wiring layer becomes deteriorated which often causes disconnection of wiring resulting in such problems as deterioration of reliability and lowering of the productive yield of semiconductor devices. In order to prevent this deterioration of reliability or lowering of productive yield, it is necessary to construct an interlayer insulation film with a completely flat structure independent of size or density of wiring width.